1. Field of Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More specifically, the present invention relates to a level shifter ESD protection circuit with power-on-sequence consideration.
2. Description of Related Art
In mixed-voltage IC, as shown in FIG. 1A, different internal circuits are supplied with power by the system voltage with different voltage levels, respectively. FIG. 1A is a block diagram of a portion of the circuit of a general mixed-voltage IC. In FIG. 1A, the operation power of the internal circuit 110 is provided by system voltage VDD1 (for example, 3.3 volts) and ground voltage VSS1 (for example, 0 volt). In addition, the operation power of the internal circuit 130 is provided by system voltage VDD2 (for example, 12 volts) and ground voltage VSS2 (for example, 0 volt). Since the input/output logic levels of the internal circuit 110 and the internal circuit 130 are different, a level shifter is needed to serve as the interface circuit of the internal circuit 110 and the internal circuit 130. For example, the level shifter 120 receives the output signal 111 (for example, 0˜3.3 volts) output by the internal circuit 110, transforms the same into a corresponding signal 131 (for example, 0˜12 volts) and outputs the same to the internal circuit 130.
When electrostatic discharge (ESD) happens at the connecting end of the mixed-voltage IC, the instantaneous ESD current would flows along the low impedance path in IC in a large volume. The large volume ESD current would generate high temperature and damage any components in the path of the current. FIG. 1B is a schematic diagram of the level shifter 120 and the ESD path in FIG. 1A. For example, as shown in FIG. 1B, when ESD event happens at the connecting end of the ground voltage VSS2, if the system voltage VDD1 is grounded, then the ESD current passes through the gate capacitor of the transistor 121 from the ground voltage line VSS2, flows to the system voltage line VDD1 (the dotted line ESD1 of the current path shown in the figure). Or, if the system voltage VSS1 is grounded, then the ESD current passes through the gate capacitor of the transistor 121 from the ground voltage line VSS2 and travels to the ground voltage line VSS1 (the dotted line ESD2 of the current path shown in the figure). As a result, the transistor 121 may be damaged (in the same principle, the transistor 122 may also be damaged).
The main cause of the damage of the above components is because there is no connection between the ground voltage line VSS1 and the ground voltage line VSS2. Therefore, the electrostatic discharge current ESD is not able to be conducted to the ground voltage line VSS2 via the ground voltage line VSS1, but only through the silicon substrate. If the substrate impedance is not small enough, the electrostatic discharge current ESD may damage the transistor 121. Since the ESD is instantaneous, therefore in the case of electrostatic discharge, the impedance of gate capacitor is less than the impedance of normal operation.
FIG. 1C is a schematic diagram of another level shifter 120 and ESD path in FIG. 1A. As shown in FIG. 1C, the gravity of regular ESD occurred in the system voltage line VDD2 is severer than the regular ESD occurred in the ground voltage line VSS2. That is because the ground voltage line VSS2 still has the substrate as the connection path connecting the ground voltage line VSS1, yet there is no discharging path in N well to help balance charge. Therefore, for example, when ESD event happens at the connecting end of the system voltage line VDD2, if system voltage VDD1 is grounded, then the electrostatic discharge current ESD travels through the gate capacitor of the transistor 123 from the system voltage line VDD2 and arrives at the system voltage line VDD1 (the dotted line ESD1 of the current path shown in FIG. 1C). Or, if the ground voltage line VSS1 is grounded, then the electrostatic discharge current ESD travels through the gate capacitor of the transistor 123 from the system voltage line VDD2 and arrives at the ground voltage line VSS1 (the dotted line ESD2 of the current path shown in FIG. 1C). As a result, the transistor 123 may be damaged (same principle, the transistor 124 may also be burned).
An ESD protection circuit (such as Taiwan Patent No. I234266) may be disposed in the level shifter 120 by those who are skilled in the art to avoid the level shifter 120 from damaged by ESD current. However, system voltage line VDD1 and system voltage line VDD2 are usually not powered on at the same time. For example, the mixed-voltage IC cuts off the power supply of the system voltage line VDD2 when entering power saving mode, while the power supply of the system voltage line VDD1 is maintained. If the power-on-sequence is taken into consideration, because of the disposition of the ESD protection circuit, the first powered-on power supply may affect the power which is not yet powered on and the related circuits thereof. For example, FIG. 1D schematically describes that, through the disposed ESD protection circuit, the power supply which has not been powered on and the related circuits are affected by the power supply which has been powered on earlier.
With reference to FIG. 1D, when the power supply of the system voltage line VDD1 is activated first before the power supply of the system voltage line VDD2, the system voltage line VDD1 supplies power to the system voltage line VDD2 via the transistor 125 and the ESD clamp circuit 126 (and/or the ESD clamp circuit 127). Therefore, the internal circuit 130 which should be turned off may be turned on because of the power supplied by the system voltage line VDD1. In addition, since the operating voltage of the internal circuit 130 is different from the voltage of the internal circuit 110, when the system voltage line VDD1 supplies power to the system voltage line VDD2 via the ESD clamp circuit, error of the internal circuit 130 will occur, and even the internal circuit 130 may be damaged.